Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), among others.
Memory devices can typically include one or more groups of one-transistor, charge storage memory cells that allow for high memory densities, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logic form in which the basic memory cell configuration of each is arranged. The charge storage memory cells can be arranged as a memory array, which is typically arranged in a matrix. The gates of each transistor based memory cell in a row of the memory array are coupled to an access line, for example, a word line in some structures. In a typical NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line, for example, a bit line in some structures. In a typical NAND architecture, the drains of each memory cell in a column of the array are coupled together in series, source to drain, between a source line and a data line.
Both NOR and NAND architecture semiconductor memory arrays are accessed through decoders that activate specific memory cells by selecting the access line coupled to their gates. In a NOR architecture semiconductor memory array, once activated, the selected memory cells place their data values on data lines, causing different currents to flow depending on the state at which a particular cell is programmed. In a typical NAND architecture semiconductor memory array, a high bias voltage is applied to a drain-side select gate (SGD) line. A signal is applied to a source select gate (SGS) line to activate (turn on) select transistors to electrically couple strings to a source line. Access lines coupled to the gates of the unselected memory cells of each group are driven at a specified pass voltage (Vpass) to operate the unselected memory cells of each group as pass transistors, for example, to pass current in a manner that is unrestricted by their stored data values. Current then flows through each series coupled group, restricted only by the selected memory cells of each group, placing current encoded data values of the row of selected memory cells on the data lines.
Each charge storage memory cell in a NOR or NAND architecture semiconductor memory array can be programmed individually or collectively to one or a number of programmed states. For example, a single-level cell (SLC) can represent one of two programmed states, for example, a “1” or a “0”, representing one bit of data. However, some memory cells can also represent one of more than two programmed states, allowing the manufacture of higher density memories without increasing the number of memory cells, as each cell can represent more than one binary digit, that is, more than one bit. Such cells can be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In certain examples, MLC can refer to a memory cell that can store two bits of data per cell, which represents one of four programmed states, and a triple-level cell (TLC) can refer to a memory cell that can store three bits of data per cell, which represents one of eight programmed states. In other examples, MLC can refer to any memory cell that can store more than one bit of data per cell, or can represent one of more than two programmed states. Each one of these programmed states can be correlated to a threshold voltage (Vt) of the charge storage memory cell, defining a level for each of the programmed states. Each cell's Vt is indicative of the data that is stored in the cell. These levels be also be referred to as a distribution, where the distribution has a number of different threshold levels at which to set the charge storage memory cell correlated to specific programmed states.
During a program algorithm in a NAND component, for example, a conventional program algorithm proceeds in a progressive manner by placing a Vt of one level of multiple levels/distribution at a time. In such a design, multiple evaluations of failure bytes are performed at every program pulse/stage, to check the Vt of the cells being programmed. This leads to inefficiency and increase in program performance, which can be represented by a time to program (tPROG).